The Design of CMOS AD Converter for High Speed Embedded System Application 


Vol. 33,  No. 5, pp. 378-385, May  2008


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  Abstract

This paper has been designed with CMOS Analog-to-Digital Converter(ADC) to use a high speed embedded system. It used flash ADC with a voltage estimator and comparator for background developed autozeroing. The speed of this architecture is almost similar to conventional flash ADC but the die size are lower due to reduced numbers of comparators and associated circuity. This ADC is implemented in a 0.25㎛ pure digital CMOS technology.

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  Cite this article

[IEEE Style]

S. Kwon, "The Design of CMOS AD Converter for High Speed Embedded System Application," The Journal of Korean Institute of Communications and Information Sciences, vol. 33, no. 5, pp. 378-385, 2008. DOI: .

[ACM Style]

Seung-Tag Kwon. 2008. The Design of CMOS AD Converter for High Speed Embedded System Application. The Journal of Korean Institute of Communications and Information Sciences, 33, 5, (2008), 378-385. DOI: .

[KICS Style]

Seung-Tag Kwon, "The Design of CMOS AD Converter for High Speed Embedded System Application," The Journal of Korean Institute of Communications and Information Sciences, vol. 33, no. 5, pp. 378-385, 5. 2008.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880