A Design of the Signal Processing Hardware Platform for OFDM Communication Systems 


Vol. 33,  No. 6, pp. 498-504, Jun.  2008


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  Abstract

In this paper, an efficient hardware platform for the digital signal processing for OFDM Communcation systems is presented. The hardware platform consists of a single FPGA, two DSPs with 8000 MIPS of maximum at 1 ㎓ clock, 2-channel ADC and DAC supporting maximum 125 ㎒ sampling rate, and flexible data bus architecture, so that a wide variety of baseband signal processing algorithms for practical OFDM communication systems may be implemented and tested. The IEEE 802.16 software modem is also presented in order to verify the effectiveness and usefulness of the designed platform.

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  Cite this article

[IEEE Style]

B. W. Lee and S. H. Cho, "A Design of the Signal Processing Hardware Platform for OFDM Communication Systems," The Journal of Korean Institute of Communications and Information Sciences, vol. 33, no. 6, pp. 498-504, 2008. DOI: .

[ACM Style]

Byung Wook Lee and Sung Ho Cho. 2008. A Design of the Signal Processing Hardware Platform for OFDM Communication Systems. The Journal of Korean Institute of Communications and Information Sciences, 33, 6, (2008), 498-504. DOI: .

[KICS Style]

Byung Wook Lee and Sung Ho Cho, "A Design of the Signal Processing Hardware Platform for OFDM Communication Systems," The Journal of Korean Institute of Communications and Information Sciences, vol. 33, no. 6, pp. 498-504, 6. 2008.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880