Design and Implementation of High-Speed Pattern Matcher in Network Intrusion Detection System 


Vol. 33,  No. 11, pp. 1020-1029, Nov.  2008


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  Abstract

This paper proposes an high speed pattern matching algorithm and its implementation. The pattern matcher is used to check patterns from realtime input packet. The proposed algorithm can find exact string, range of string values, and combination of string values from input packet at high speed. Given string and rule set are modelled as a state transition graph which can find overlapped strings simultaneously, and the state transition graph is partitioned according to input implicants to reduce implementation complexity. The pattern matcher scheme uses the transformed state transition graph and input packet as an input. The pattern matcher was modelled and implemented in VHDL language. Experimental results show the proprieties of the proposed approach.

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  Cite this article

[IEEE Style]

Y. Yoon and S. Hwang, "Design and Implementation of High-Speed Pattern Matcher in Network Intrusion Detection System," The Journal of Korean Institute of Communications and Information Sciences, vol. 33, no. 11, pp. 1020-1029, 2008. DOI: .

[ACM Style]

Yeo-Chan Yoon and Sun-Young Hwang. 2008. Design and Implementation of High-Speed Pattern Matcher in Network Intrusion Detection System. The Journal of Korean Institute of Communications and Information Sciences, 33, 11, (2008), 1020-1029. DOI: .

[KICS Style]

Yeo-Chan Yoon and Sun-Young Hwang, "Design and Implementation of High-Speed Pattern Matcher in Network Intrusion Detection System," The Journal of Korean Institute of Communications and Information Sciences, vol. 33, no. 11, pp. 1020-1029, 11. 2008.