Parallel Processing Architecture for Parity Checksum Generator Complying with ITU-T J.83 ANNEX B 


Vol. 34,  No. 6, pp. 619-625, Jun.  2009


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  Abstract

This paper proposes a parallel architecture of a Parity Checksum Generator adopted for packet synchronization and error detection in the ITU-T Recommendation J.83 Annex B. The proposed parallel processing architecture removes a performance bottleneck occurred in a conventional serial processing architecture, leading to significant decrease in processing time for generating a Parity Checksum. The implementation results show that the proposed parallel processing architecture reduces the processing time by 83.1% at the expense of 16% area increase.

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  Cite this article

[IEEE Style]

J. Lee, E. Hong, D. Har, H. Lim, "Parallel Processing Architecture for Parity Checksum Generator Complying with ITU-T J.83 ANNEX B," The Journal of Korean Institute of Communications and Information Sciences, vol. 34, no. 6, pp. 619-625, 2009. DOI: .

[ACM Style]

Jong-yeop Lee, Eon-pyo Hong, Dong-soo Har, and Hoi-Jeong Lim. 2009. Parallel Processing Architecture for Parity Checksum Generator Complying with ITU-T J.83 ANNEX B. The Journal of Korean Institute of Communications and Information Sciences, 34, 6, (2009), 619-625. DOI: .

[KICS Style]

Jong-yeop Lee, Eon-pyo Hong, Dong-soo Har, Hoi-Jeong Lim, "Parallel Processing Architecture for Parity Checksum Generator Complying with ITU-T J.83 ANNEX B," The Journal of Korean Institute of Communications and Information Sciences, vol. 34, no. 6, pp. 619-625, 6. 2009.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880