Channel Modeling for Multi-Level Cell Memory 


Vol. 34,  No. 9, pp. 880-886, Sep.  2009


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  Abstract

Recently, the memory is used in many electronic devices, thus, the many researchers make a study of the memory. To increase a storage capacity per memory block, the researchers study for reducing the fabrication process of memory and multi-level cell memory which is storing more than 2-bits in a cell. However, the multi-level cell memory has low bit-error rates by various noises. In this paper, we study the noise of multi-level cell memory, and we propose the channel model of multi-level cell memory.

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  Cite this article

[IEEE Style]

D. Park and J. Lee, "Channel Modeling for Multi-Level Cell Memory," The Journal of Korean Institute of Communications and Information Sciences, vol. 34, no. 9, pp. 880-886, 2009. DOI: .

[ACM Style]

Donghyuk Park and Jaejin Lee. 2009. Channel Modeling for Multi-Level Cell Memory. The Journal of Korean Institute of Communications and Information Sciences, 34, 9, (2009), 880-886. DOI: .

[KICS Style]

Donghyuk Park and Jaejin Lee, "Channel Modeling for Multi-Level Cell Memory," The Journal of Korean Institute of Communications and Information Sciences, vol. 34, no. 9, pp. 880-886, 9. 2009.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880