An Efficient Architecture Exploration for Embedded Core Design Exploiting Design Hierarchy 


Vol. 35,  No. 12, pp. 1758-1765, Dec.  2010


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  Abstract

This paper proposes an architecture exploration methodology for the design of embedded cores exploiting design hierarchy. The proposed method performs systematic architecture exploration by taking different approaches for verifying designs and estimating performances depending on the hierarchy level in design process. Performance estimation tools generate profile having performance data related with design modules of an embedded core. Profile analyzer performs data-mining to acquire association rules between the design modules and performance parameters. Inference engine in the profile analyzer updates the association rules which will be used to improve the design performance at next exploration steps. To show the efficiency of the proposed architecture explorations methodology, experiments had been performed for JPEG encoder, Chen-DCT, and FFT application functions. The embedded cores designed by taking the proposed method show performance improvement by 60.8% in terms of clock cycles on the average when compared with the initial embedded core in MIPS R3000.

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  Cite this article

[IEEE Style]

S. Kim and S. Hwang, "An Efficient Architecture Exploration for Embedded Core Design Exploiting Design Hierarchy," The Journal of Korean Institute of Communications and Information Sciences, vol. 35, no. 12, pp. 1758-1765, 2010. DOI: .

[ACM Style]

Sang-Woo Kim and Sun-Young Hwang. 2010. An Efficient Architecture Exploration for Embedded Core Design Exploiting Design Hierarchy. The Journal of Korean Institute of Communications and Information Sciences, 35, 12, (2010), 1758-1765. DOI: .

[KICS Style]

Sang-Woo Kim and Sun-Young Hwang, "An Efficient Architecture Exploration for Embedded Core Design Exploiting Design Hierarchy," The Journal of Korean Institute of Communications and Information Sciences, vol. 35, no. 12, pp. 1758-1765, 12. 2010.