Optimizing the Circuit for Finding 2 Error Positions of 2 Error Correcting Reed Solomon Decoder 


Vol. 36,  No. 1, pp. 8-13, Jan.  2011


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  Abstract

In this paper, we show new method to find error locations of 2 eight bit symbol errors for 2 error correcting Reed-Solomon decoder. New design is much faster and has much simpler logic circuit than the former design method. This optimization was possible by partitioning the 8 bit operations into 4 bit arithgmatic and logic operations. This Reed Solomon decoder can be used for data protection of almost all digital communication and consumer electronic devices.

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  Cite this article

[IEEE Style]

H. An, "Optimizing the Circuit for Finding 2 Error Positions of 2 Error Correcting Reed Solomon Decoder," The Journal of Korean Institute of Communications and Information Sciences, vol. 36, no. 1, pp. 8-13, 2011. DOI: .

[ACM Style]

Hyeong-Keon An. 2011. Optimizing the Circuit for Finding 2 Error Positions of 2 Error Correcting Reed Solomon Decoder. The Journal of Korean Institute of Communications and Information Sciences, 36, 1, (2011), 8-13. DOI: .

[KICS Style]

Hyeong-Keon An, "Optimizing the Circuit for Finding 2 Error Positions of 2 Error Correcting Reed Solomon Decoder," The Journal of Korean Institute of Communications and Information Sciences, vol. 36, no. 1, pp. 8-13, 1. 2011.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880