The Design of Hardware MPI Units for MPSoC 


Vol. 36,  No. 1, pp. 86-92, Jan.  2011


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  Abstract

In this paper, we propose a novel hardware MPI(Message Passing Interface) unit which supports message passing in multiprocessor system which use distributed memory architecture. MPI Hardware unit processes data synchronization, transmission and completion, and it supports processor non-blocking operation so it reduces overhead according to synchronization. Additionally, MPI hardware unit combines ready entry, request entry, reserve entry which save and manage the synchronized messages and performs the multiple outstanding issue and out of order completion. According to BFM(Bus Functional Model) simulation result, the performance is increased by 25% on many to many communication. After we designed MPI unit using HDL, with synopsys design compiler we synthesized, and for synthesis library we used MagnaChip 0.18㎛. And then we making prototype chip. The proposed message transmission interface hardware shows high performance for its increase in size. Thus, as we consider low-cost design and scalability, MPI hardware unit is useful in increasing overall performance of embedded MPSoC(Multi-Processor System-on-Chip).

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  Cite this article

[IEEE Style]

H. Jeong, W. Chung, Y. Lee, "The Design of Hardware MPI Units for MPSoC," The Journal of Korean Institute of Communications and Information Sciences, vol. 36, no. 1, pp. 86-92, 2011. DOI: .

[ACM Style]

Hayoung Jeong, Wonyoung Chung, and Yong-surk Lee. 2011. The Design of Hardware MPI Units for MPSoC. The Journal of Korean Institute of Communications and Information Sciences, 36, 1, (2011), 86-92. DOI: .

[KICS Style]

Hayoung Jeong, Wonyoung Chung, Yong-surk Lee, "The Design of Hardware MPI Units for MPSoC," The Journal of Korean Institute of Communications and Information Sciences, vol. 36, no. 1, pp. 86-92, 1. 2011.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880