Design of Degree-Computationless Modified Euclidean Algorithm using Polynomial Expression 


Vol. 36,  No. 10, pp. 809-815, Oct.  2011


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  Abstract

In this paper, we have proposed and implemented a novel architecture which can be used to effectively design the modified Euclidean (ME) algorithm for key equation solver (KES) block in high-speed Reed-Solomon (RS) decoder. With polynomial expressions of newly-defined state variables for controlling each processing element (PE), the proposed architecture has simple input/output signals and requires less hardware complexity because no degree computation circuits are needed. In addition, since each PE circuit is independent of the error correcting capability ? of RS codes, it has the advantage of linearly increase of the hardware complexity of KES block as ? increases. For comparisons, KES block for RS(255,239,8) decoder is implemented using Verilog HDL and synthesized with 0.13um CMOS cell library. From the results, we can see that the propesed architecture can be used for a high-speed RS decoder with less gate count.

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  Cite this article

[IEEE Style]

S. Kang and N. Y. Kim, "Design of Degree-Computationless Modified Euclidean Algorithm using Polynomial Expression," The Journal of Korean Institute of Communications and Information Sciences, vol. 36, no. 10, pp. 809-815, 2011. DOI: .

[ACM Style]

Sung-Jin Kang and Nam Yong Kim. 2011. Design of Degree-Computationless Modified Euclidean Algorithm using Polynomial Expression. The Journal of Korean Institute of Communications and Information Sciences, 36, 10, (2011), 809-815. DOI: .

[KICS Style]

Sung-Jin Kang and Nam Yong Kim, "Design of Degree-Computationless Modified Euclidean Algorithm using Polynomial Expression," The Journal of Korean Institute of Communications and Information Sciences, vol. 36, no. 10, pp. 809-815, 10. 2011.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880