Design Optimization of the Arithmatic Logic Unit Circuit for the Processor to Determine the Number of Errors in the Reed Solomon Decoder 


Vol. 36,  No. 11, pp. 649-654, Nov.  2011


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  Abstract

In this paper, we show new method to find number of errors in the Reed-Solomon decoder. New design is much faster and has much simpler logic circuit than the former design method. This optimization was possible by very simplified square calculating circuit and parallel processing. The microcontroller of this Reed Solomon decoder can be used for data protection of almost all digital communication and consumer electronic devices.

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  Cite this article

[IEEE Style]

H. An, "Design Optimization of the Arithmatic Logic Unit Circuit for the Processor to Determine the Number of Errors in the Reed Solomon Decoder," The Journal of Korean Institute of Communications and Information Sciences, vol. 36, no. 11, pp. 649-654, 2011. DOI: .

[ACM Style]

Hyeong-Keon An. 2011. Design Optimization of the Arithmatic Logic Unit Circuit for the Processor to Determine the Number of Errors in the Reed Solomon Decoder. The Journal of Korean Institute of Communications and Information Sciences, 36, 11, (2011), 649-654. DOI: .

[KICS Style]

Hyeong-Keon An, "Design Optimization of the Arithmatic Logic Unit Circuit for the Processor to Determine the Number of Errors in the Reed Solomon Decoder," The Journal of Korean Institute of Communications and Information Sciences, vol. 36, no. 11, pp. 649-654, 11. 2011.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880