Design 5Q MPI Hardware Unit Supporting Standard Mode 


Vol. 37,  No. 1, pp. 59-66, Jan.  2012


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  Abstract

The use of MPSoC has been increasing because of a rise of use of mobile devices and complex applications. For improving the performance of MPSoC, number of processor has been increasing. Standard MPI is used for efficiently sending data in distributed memory architecture that has advantage in multi processor. Standard In this paper, we propose a scalable distributed memory system with a low cost hardware message passing interface(MPI). The proposed architecture improves transfer rate with buffered send for small size packet. Three queues, Ready Queue, Request Queue, and Reservation Queue, work as previous architecture, and two queues, Small Ready Queue and Small Request Queue, are added to send small size packet. When the critical point is set 8 bytes, the proposed architecture takes more than 2 times the performance improvement in the data that below the critical point.

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  Cite this article

[IEEE Style]

J. W. Park, W. Y. Chung, S. W. Lee, Y. S. Lee, "Design 5Q MPI Hardware Unit Supporting Standard Mode," The Journal of Korean Institute of Communications and Information Sciences, vol. 37, no. 1, pp. 59-66, 2012. DOI: .

[ACM Style]

Jae Won Park, Won Young Chung, Seung Woo Lee, and Yong Surk Lee. 2012. Design 5Q MPI Hardware Unit Supporting Standard Mode. The Journal of Korean Institute of Communications and Information Sciences, 37, 1, (2012), 59-66. DOI: .

[KICS Style]

Jae Won Park, Won Young Chung, Seung Woo Lee, Yong Surk Lee, "Design 5Q MPI Hardware Unit Supporting Standard Mode," The Journal of Korean Institute of Communications and Information Sciences, vol. 37, no. 1, pp. 59-66, 1. 2012.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880