Implementation of 40 Gb/s Network Processor of Wire-Speed Flow Management 


Vol. 37,  No. 9, pp. 814-821, Sep.  2012


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  Abstract

We propose a network processor called an OmniFlow processor capable of wire-speed flow management by a hardware-based flow admission control(FAC) in this paper. Because the OmniFlow processor can set up and release a wire-speed connection for flows, the update period of flows can be set to a short time, and only active flows can be effectively managed by terminating a flow that does not have a packet transmitted within this period. Therefore, the FAC can be used to provide a reliable transmission of UDP as well as TCP applications. This processor is fabricated in 65nm CMOS technology, and total gate count is 25 million. It has 40 Gb/s throughput performance in using the 32 RISC cores when maximum operating frequency is 555MHz.

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  Cite this article

[IEEE Style]

K. Doo, B. Lee, W. Kim, "Implementation of 40 Gb/s Network Processor of Wire-Speed Flow Management," The Journal of Korean Institute of Communications and Information Sciences, vol. 37, no. 9, pp. 814-821, 2012. DOI: .

[ACM Style]

Kyeong-Hwan Doo, Bhum-Cheol Lee, and Whan-Woo Kim. 2012. Implementation of 40 Gb/s Network Processor of Wire-Speed Flow Management. The Journal of Korean Institute of Communications and Information Sciences, 37, 9, (2012), 814-821. DOI: .

[KICS Style]

Kyeong-Hwan Doo, Bhum-Cheol Lee, Whan-Woo Kim, "Implementation of 40 Gb/s Network Processor of Wire-Speed Flow Management," The Journal of Korean Institute of Communications and Information Sciences, vol. 37, no. 9, pp. 814-821, 9. 2012.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880