Design of Core Chip for 3.1Gb/s VCSEL Driver in 0.18㎛ CMOS 


Vol. 38,  No. 1, pp. 88-95, Jan.  2013


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  Abstract

We propose a novel driver circuit design using 0.18㎛ CMOS process technology that drives a 1550 ㎚ high-speed VCSEL used in optical transceiver. We report a distinct improvement in bandwidth, voltage gain and eye diagram at 3.1Gb/s data rate in comparison with existing topology. In this paper, the design and layout of a 3.1Gb/s VCSEL driver for optical transceiver having arrayed multi-channel of integrating module is confirmed.

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  Cite this article

[IEEE Style]

C. Yang and S. Lee, "Design of Core Chip for 3.1Gb/s VCSEL Driver in 0.18㎛ CMOS," The Journal of Korean Institute of Communications and Information Sciences, vol. 38, no. 1, pp. 88-95, 2013. DOI: .

[ACM Style]

Choong-reol Yang and Sang-soo Lee. 2013. Design of Core Chip for 3.1Gb/s VCSEL Driver in 0.18㎛ CMOS. The Journal of Korean Institute of Communications and Information Sciences, 38, 1, (2013), 88-95. DOI: .

[KICS Style]

Choong-reol Yang and Sang-soo Lee, "Design of Core Chip for 3.1Gb/s VCSEL Driver in 0.18㎛ CMOS," The Journal of Korean Institute of Communications and Information Sciences, vol. 38, no. 1, pp. 88-95, 1. 2013.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880