A High Speed LDPC Decoder Structure Based on the HSS 


Vol. 38,  No. 2, pp. 140-145, Feb.  2013


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  Abstract

This paper proposes the high speed LDPC decoder structure base on the DVB-S2. Firstly, We study the solution to avoid the memory conflict. For the high speed decoding process the decoder adapts the HSS(Horizontal Shuffle Scheduling) scheme. Secondly, for the high speed decoding algorithm normalized Min-Sum algorithm is adapted instead of Sum-Product algorithm. And the self corrected is a variant of the LDPC decoding that sets the reliability of a Mc→v message to 0 if there is an inconsistency between the signs of the current incoming messages Mv’→c and the sign of the previous incoming messages Moldv’→c This self-corrected algorithm avoids the propagation on unreliable information in the Tanner graph and thus, helps the convergence of the decoder.Start after striking space key 2 times. Lastly, and this paper propose the optimal hardware architecture supporting the high speed throughput.

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  Cite this article

[IEEE Style]

I. Lee, M. Kim, D. Oh, J. Jung, "A High Speed LDPC Decoder Structure Based on the HSS," The Journal of Korean Institute of Communications and Information Sciences, vol. 38, no. 2, pp. 140-145, 2013. DOI: .

[ACM Style]

In-Ki Lee, Min-Hyuk Kim, Deock-Gil Oh, and Ji-Won Jung. 2013. A High Speed LDPC Decoder Structure Based on the HSS. The Journal of Korean Institute of Communications and Information Sciences, 38, 2, (2013), 140-145. DOI: .

[KICS Style]

In-Ki Lee, Min-Hyuk Kim, Deock-Gil Oh, Ji-Won Jung, "A High Speed LDPC Decoder Structure Based on the HSS," The Journal of Korean Institute of Communications and Information Sciences, vol. 38, no. 2, pp. 140-145, 2. 2013.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880