Development and Verification of Digital EEG Signal Transmission Protocol 


Vol. 38,  No. 7, pp. 623-629, Jul.  2013


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  Abstract

This paper presents the implementation result of the EEG(electroencephalogram) signal transmission protocol and its test platform. EEG measured by a dry-type electrode is directly converted into digital signal by ADC(analog-to-digital converter). Thereafter it is transferred DSP(digital signal processor) platform by I<SUP>2</SUP>C(inter-integrated circuit) protocol. DSP conducts the pre-processing of EEG and extracts feature vectors of EEG. In this work, we implement the I<SUP>2</SUP>C protocol with 16 channels by using 10 or 12-bit ADC. In the implementation results, the overhead ratio for the 4 bytes data burst transmission measures 2.16 and the total data rates are 345.6 kbps and 414.72 kbps with 10-bit and 12-bit 1 ksps ADC, respectively. Therefore, in order to support a high speed mode of I<SUP>2</SUP>C for 400 kbps, it is required to use 16:1 and (8:1)×2 ratios for slave:master in 10-bit ADC and 12-bit ADC, respectively.

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  Cite this article

[IEEE Style]

D. Kim and K. Hwang, "Development and Verification of Digital EEG Signal Transmission Protocol," The Journal of Korean Institute of Communications and Information Sciences, vol. 38, no. 7, pp. 623-629, 2013. DOI: .

[ACM Style]

Do-Hoon Kim and Kyu-Sung Hwang. 2013. Development and Verification of Digital EEG Signal Transmission Protocol. The Journal of Korean Institute of Communications and Information Sciences, 38, 7, (2013), 623-629. DOI: .

[KICS Style]

Do-Hoon Kim and Kyu-Sung Hwang, "Development and Verification of Digital EEG Signal Transmission Protocol," The Journal of Korean Institute of Communications and Information Sciences, vol. 38, no. 7, pp. 623-629, 7. 2013.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880