An Efficient Wear-Leveling Algorithm for NAND Flash SSD with Multi-Channel and Multi-Way Architecture 


Vol. 39,  No. 7, pp. 425-432, Jul.  2014


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  Abstract

This paper proposes a wear-leveling algorithm that exploits the properties of SSD memories with multi-channel and multi-way architecture. When a write request arrives, the proposed algorithm classifies the stored data in DRAM buffer into hot or cold according to logical address access frequency, and performs data allocation to reduce deviation of block erase counts. It lowers the chance of increasing erase count by allocating cold data to blocks which have high erase count. Effectiveness of the proposed algorithm is verified by executing various applications on a multi-channel, multi-way SSD simulator. Experimental results show that differences in erase count among blocks is reduced by an average of 9.3%, and total erase count decreases by 4.6%, when compared to previous wear-leveling algorithm.

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  Cite this article

[IEEE Style]

D. Kim and S. Hwang, "An Efficient Wear-Leveling Algorithm for NAND Flash SSD with Multi-Channel and Multi-Way Architecture," The Journal of Korean Institute of Communications and Information Sciences, vol. 39, no. 7, pp. 425-432, 2014. DOI: .

[ACM Style]

Dong-ho Kim and Sun-young Hwang. 2014. An Efficient Wear-Leveling Algorithm for NAND Flash SSD with Multi-Channel and Multi-Way Architecture. The Journal of Korean Institute of Communications and Information Sciences, 39, 7, (2014), 425-432. DOI: .

[KICS Style]

Dong-ho Kim and Sun-young Hwang, "An Efficient Wear-Leveling Algorithm for NAND Flash SSD with Multi-Channel and Multi-Way Architecture," The Journal of Korean Institute of Communications and Information Sciences, vol. 39, no. 7, pp. 425-432, 7. 2014.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880