A Design and Implementation of 4×10 Gb/s Transimpedance Amplifiers (TIA) Array for TWDM-PON 


Vol. 39,  No. 7, pp. 440-448, Jul.  2014


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  Abstract

A 4×10 Gb/s Transimpedance Amplifier (TIA) array is implemented in 0.13 μm CMOS process technology, which will be used in the receiver of TWDM-PON system. A technology for bandwidth enhancement of a given 4×10 Gb/s TIA presented under inductor peaking technology and a single 1.2V power supply based low voltage design technology. It achieves 3 dB bandwidth of 7 GHz in the presence of a 0.5 pF photodiode capacitance. The trans-resistance gain is 50 dBΩ, while 48 mW/ 1channel from a 1.2 V supply. The input sensitivity of the TIA is -27 dBm. The chip size is 1.9 mm × 2.2 mm.

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  Cite this article

[IEEE Style]

C. Yang, K. Lee, S. Lee, "A Design and Implementation of 4×10 Gb/s Transimpedance Amplifiers (TIA) Array for TWDM-PON," The Journal of Korean Institute of Communications and Information Sciences, vol. 39, no. 7, pp. 440-448, 2014. DOI: .

[ACM Style]

Choong-reol Yang, Kang-yoon Lee, and Sang-soo Lee. 2014. A Design and Implementation of 4×10 Gb/s Transimpedance Amplifiers (TIA) Array for TWDM-PON. The Journal of Korean Institute of Communications and Information Sciences, 39, 7, (2014), 440-448. DOI: .

[KICS Style]

Choong-reol Yang, Kang-yoon Lee, Sang-soo Lee, "A Design and Implementation of 4×10 Gb/s Transimpedance Amplifiers (TIA) Array for TWDM-PON," The Journal of Korean Institute of Communications and Information Sciences, vol. 39, no. 7, pp. 440-448, 7. 2014.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880