Hardware Design of Bilateral Filter Based on Window Division 


Vol. 41,  No. 12, pp. 1844-1850, Dec.  2016


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  Abstract

The bilateral filter can reduce the noise while preserving details computing the filtering output at each pixels as the average of neighboring pixels. In this paper, we propose a real-time system based on window division. Overall performance is increased due to the parallel architectures which computes five rows in the kernel window simultaneously but with pipelined scheduling. We consider the tradeoff between the filter performance and the hardware cost and the bit allocation has been determined by PSNR analysis. The proposed architecture is designed with verilogHDL and synthesized using Dongbu Hitek 110㎚ standard cell library. The proposed architecture shows 416Mpixels/s (397fps) of throughput at 416㎒ of operating frequency with 132K gates.

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  Cite this article

[IEEE Style]

Y. Hyun and T. Park, "Hardware Design of Bilateral Filter Based on Window Division," The Journal of Korean Institute of Communications and Information Sciences, vol. 41, no. 12, pp. 1844-1850, 2016. DOI: .

[ACM Style]

Yongho Hyun and Taegeun Park. 2016. Hardware Design of Bilateral Filter Based on Window Division. The Journal of Korean Institute of Communications and Information Sciences, 41, 12, (2016), 1844-1850. DOI: .

[KICS Style]

Yongho Hyun and Taegeun Park, "Hardware Design of Bilateral Filter Based on Window Division," The Journal of Korean Institute of Communications and Information Sciences, vol. 41, no. 12, pp. 1844-1850, 12. 2016.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880