Design of a Low-Power LDPC Decoder by Reducing Decoding Iterations 


Vol. 32,  No. 9, pp. 801-809, Sep.  2007


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  Abstract

LDPC (Low Density Parity Check) code, which is an error correcting code determined to be applied to the 4th generation mobile communication systems, requires a heavy computational complexity due to iterative decodings to achieve a high BER performance. This paper proposes an algorithm to reduce the number of decoding iterations to increase performance of the decoder in decoding latency and power consumption. Measuring changes between the current decoded LLR values and previous ones, the proposed algorithm predicts directions of the value changes. Based on the prediction, the algorithm inverts the sign bits of the LLR values to speed up convergence, which means parity check equation is satisfied. Simulation results show that the number of iterations has been reduced by about 33% without BER performance degradation in the proposed decoder, and the power consumption has also been decreased in proportional to the amount of the reduced decoding iterations.

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  Cite this article

[IEEE Style]

J. Lee, C. Park, S. Hwang, "Design of a Low-Power LDPC Decoder by Reducing Decoding Iterations," The Journal of Korean Institute of Communications and Information Sciences, vol. 32, no. 9, pp. 801-809, 2007. DOI: .

[ACM Style]

Jun-Ho Lee, Chang-Soo Park, and Sun-Young Hwang. 2007. Design of a Low-Power LDPC Decoder by Reducing Decoding Iterations. The Journal of Korean Institute of Communications and Information Sciences, 32, 9, (2007), 801-809. DOI: .

[KICS Style]

Jun-Ho Lee, Chang-Soo Park, Sun-Young Hwang, "Design of a Low-Power LDPC Decoder by Reducing Decoding Iterations," The Journal of Korean Institute of Communications and Information Sciences, vol. 32, no. 9, pp. 801-809, 9. 2007.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880