An Efficient Kernel-based Partitioning Algorithm for Low-power , Low-area Logic Circuit Design
Vol. 25, No. 8, pp. 1477-1486, Aug. 2000
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Cite this article
[IEEE Style]
황선영, 김형, 최익성, 정기조, "An Efficient Kernel-based Partitioning Algorithm for Low-power , Low-area Logic Circuit Design," The Journal of Korean Institute of Communications and Information Sciences, vol. 25, no. 8, pp. 1477-1486, 2000. DOI: .
[ACM Style]
황선영, 김형, 최익성, and 정기조. 2000. An Efficient Kernel-based Partitioning Algorithm for Low-power , Low-area Logic Circuit Design. The Journal of Korean Institute of Communications and Information Sciences, 25, 8, (2000), 1477-1486. DOI: .
[KICS Style]
황선영, 김형, 최익성, 정기조, "An Efficient Kernel-based Partitioning Algorithm for Low-power , Low-area Logic Circuit Design," The Journal of Korean Institute of Communications and Information Sciences, vol. 25, no. 8, pp. 1477-1486, 8. 2000.
pISSN : 1226 - 4717
eISSN : 2287 - 3880