Implementation of 234.7 MHz Mixed Mode Frequency Multiplication & Distribution ASIC 


Vol. 28,  No. 11, pp. 929-935, Nov.  2003


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  Abstract

An analog/digital mixed mode ASIC for network synchronization of ATM switching system has been designed and fabricated. This ASIC generates a 234.7/46.94 MHz system clock and 77.76/19.44 MHz user clock using 46.94 MHz transmitted clocks from other systems. It also includes digital circuits for checking and selecting of the transmitted clocks. For effective ASIC design, full custom technique is used in 2 analog PLL circuits design. and standard cell based technique is used in digital circuit design. Resistors and capacitors for analog circuits are specially designed which can be fabricated in general CMOS technology, so the chip can be implemented in 0.8 ㎛ digital CMOS technology with no expensive. Testing results show stable 234.7 MHz and 19.44 MHz clocks generation with each 4 ps and 17 ps of low nos jitter.

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  Cite this article

[IEEE Style]

K. Kwon, S. Chai, H. Jung, "Implementation of 234.7 MHz Mixed Mode Frequency Multiplication & Distribution ASIC," The Journal of Korean Institute of Communications and Information Sciences, vol. 28, no. 11, pp. 929-935, 2003. DOI: .

[ACM Style]

Kwang-Ho Kwon, Sang-Hoon Chai, and Hee-Bum Jung. 2003. Implementation of 234.7 MHz Mixed Mode Frequency Multiplication & Distribution ASIC. The Journal of Korean Institute of Communications and Information Sciences, 28, 11, (2003), 929-935. DOI: .

[KICS Style]

Kwang-Ho Kwon, Sang-Hoon Chai, Hee-Bum Jung, "Implementation of 234.7 MHz Mixed Mode Frequency Multiplication & Distribution ASIC," The Journal of Korean Institute of Communications and Information Sciences, vol. 28, no. 11, pp. 929-935, 11. 2003.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880