Hardware Implementation of Integer Transform and Quantization of H.264 


Vol. 28,  No. 12, pp. 1182-1191, Dec.  2003


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  Abstract

In this paper, we propose a new hardware architecture for integer transform, quantizer, inverse quantizer, and inverse integer transform of a new video coding standard H.264/JVT. We describe the algorithm and derive hardware architecture emphasizing the importance of area for low cost and low power consumption. The proposed architecture has been verified by PCI-interfaced emulation board using APEX-Ⅱ Altera FPGA and also by ASIC synthesis using Samsung 0.18 um CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 100MHz, prodessing more than 1,300 QCIF video frames per second. The hardware is going to be used as a core module when implementing a complete H.164 video encoder/decoder ASIC for real-time multimedia application.

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  Cite this article

[IEEE Style]

Y. Lim and Y. Jeong, "Hardware Implementation of Integer Transform and Quantization of H.264," The Journal of Korean Institute of Communications and Information Sciences, vol. 28, no. 12, pp. 1182-1191, 2003. DOI: .

[ACM Style]

Young-Hun Lim and Yong-Jin Jeong. 2003. Hardware Implementation of Integer Transform and Quantization of H.264. The Journal of Korean Institute of Communications and Information Sciences, 28, 12, (2003), 1182-1191. DOI: .

[KICS Style]

Young-Hun Lim and Yong-Jin Jeong, "Hardware Implementation of Integer Transform and Quantization of H.264," The Journal of Korean Institute of Communications and Information Sciences, vol. 28, no. 12, pp. 1182-1191, 12. 2003.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880