Design of a Low Power Turbo Decoder by Reducing Decoding Iterations 


Vol. 29,  No. 1, pp. 1-8, Jan.  2004


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  Abstract

This paper proposes a novel algorithm for a low power turbo decoder based on reduction of number of decoding iterations, targeting power-critical mobile communication devices. Previous researches that attempt to reduce number of decoding iterations, such as CRC-aided and LLR methods, either show degraded BER performance in return for reduced complexity or require additional hardware resources for controlling the number of iterations to meet BER performance, respectively. The proposed algorithm can reduce power consumption without degrading the BER performance, and it is achieved with minimal hardware overhead. The proposed algorithm achieves this by comparing consecutive hard decision results using a simple buffer and counter. Simulation results show that the number of decoding iterations can be reduced to about 60% without degrading the BER performance in the proposed decoder, and power consumption can be saved in proportion to the number of decoding iterations.

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  Cite this article

[IEEE Style]

S. Back, S. Kim, S. Hwang, "Design of a Low Power Turbo Decoder by Reducing Decoding Iterations," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 1, pp. 1-8, 2004. DOI: .

[ACM Style]

Seo-Young Back, Sik Kim, and Sun-Young Hwang. 2004. Design of a Low Power Turbo Decoder by Reducing Decoding Iterations. The Journal of Korean Institute of Communications and Information Sciences, 29, 1, (2004), 1-8. DOI: .

[KICS Style]

Seo-Young Back, Sik Kim, Sun-Young Hwang, "Design of a Low Power Turbo Decoder by Reducing Decoding Iterations," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 1, pp. 1-8, 1. 2004.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880