Design of a GFAU(Galois Field Arithmetic Unit) in GF(2m) 


Vol. 28,  No. 2, pp. 80-85, Feb.  2003


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  Abstract

This paper proposes Galois Field Arithmetic Unit(GFAU) whose structure does addition, multiplication and division in GF(2m). GFAU can execute maximum two additions, or two multiplications, or one addition and one multiplication. The base architecture of this GFAU is a divider based on modified Euclid's algorithm. The divider was modified to enable multiplication and addition, and the modified divider with the control logic became GFAU. The GFAU for GF(2193) was implemented with Verilog HDL with top-down methodology, and it was improved and verified by a cycle-based simulator written in C-language. The verified model was synthesized with Samsung 0.35um, 3.3V CMOS standard cell library, and it operates at 104.7㎒ in the worst case of 3.0V, 85℃, and it has about 25,889 gates.

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  Cite this article

[IEEE Style]

M. Kim and Y. Lee, "Design of a GFAU(Galois Field Arithmetic Unit) in GF(2m)," The Journal of Korean Institute of Communications and Information Sciences, vol. 28, no. 2, pp. 80-85, 2003. DOI: .

[ACM Style]

Moon-Gyung Kim and Yong-Surk Lee. 2003. Design of a GFAU(Galois Field Arithmetic Unit) in GF(2m). The Journal of Korean Institute of Communications and Information Sciences, 28, 2, (2003), 80-85. DOI: .

[KICS Style]

Moon-Gyung Kim and Yong-Surk Lee, "Design of a GFAU(Galois Field Arithmetic Unit) in GF(2m)," The Journal of Korean Institute of Communications and Information Sciences, vol. 28, no. 2, pp. 80-85, 2. 2003.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880