Low System Complexity Parallel Multiplier for a Class of Finite Fields based on AOP 


Vol. 29,  No. 3, pp. 331-336, Mar.  2004


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  Abstract

This study focuses on the hardware implementation of fast and low-system-complexity multiplier over GF(2"'). From the properties of an irreducible AOP of degree m, the modular reduction in GF(2"') multiplicative operation can be simplified using cyclic shift operation. And then, GF(2'") multiplicative operation can be established using the array structure of AND and XOR gates. The proposed multiplier is composed of m(m+ 1) 2-input AND gates and (m+1)² 2-input XOR gates. And the minimum critical path delay is TA+[ log₂m] Tx. Proposed multiplier obtained have low circuit complexity and delay time, and the interconnections of the circuit are regular, well-suited for VLSI realization.

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  Cite this article

[IEEE Style]

G. Byun, G. Na, B. Yoon, Y. Choi, S. Han, H. Kim, "Low System Complexity Parallel Multiplier for a Class of Finite Fields based on AOP," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 3, pp. 331-336, 2004. DOI: .

[ACM Style]

Gi-Young Byun, Gi-Su Na, Byung-Hee Yoon, Young-Hee Choi, Sung-Il Han, and Heung-Soo Kim. 2004. Low System Complexity Parallel Multiplier for a Class of Finite Fields based on AOP. The Journal of Korean Institute of Communications and Information Sciences, 29, 3, (2004), 331-336. DOI: .

[KICS Style]

Gi-Young Byun, Gi-Su Na, Byung-Hee Yoon, Young-Hee Choi, Sung-Il Han, Heung-Soo Kim, "Low System Complexity Parallel Multiplier for a Class of Finite Fields based on AOP," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 3, pp. 331-336, 3. 2004.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880