A Study on the Design of Highly Parallel Multiplier using VCGM 


Vol. 27,  No. 6, pp. 555-561, Jun.  2002


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  Abstract

In this paper, a new designed circuit of highly parallel multiplier using standard basis over GF(2??) is presented. Prior to construct the multiplier circuit, we provide the Vector Code Generate Module(VCGM) that generate each vector codes for multiplication. Using these VCGMs, we can get all vector codes necessary for operation and modular sum up each independent corresponding basis, respectively. Following the equations in this paper, we can design generalized multiplier to m. For the proposed circuit in this paper, we show the example in GF(2⁴) using VCGMs. In this paper, we build a multiplier with VCGMs, AND blocks, and EX-OR blocks. Therefore the proposed circuit is easy to generalize for m and advantageous for VLSI. Also, it need no memory element and the latency not less fewer then other circuit. We verify the proposed circuit by functional simulation and show its result. Finally, we compare the circuit composition with other works and show its result with a table.

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  Cite this article

[IEEE Style]

G. Byun, H. Seong, H. Kim, "A Study on the Design of Highly Parallel Multiplier using VCGM," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 6, pp. 555-561, 2002. DOI: .

[ACM Style]

Gi-Young Byun, Hyeon-Kyeong Seong, and Heung-Soo Kim. 2002. A Study on the Design of Highly Parallel Multiplier using VCGM. The Journal of Korean Institute of Communications and Information Sciences, 27, 6, (2002), 555-561. DOI: .

[KICS Style]

Gi-Young Byun, Hyeon-Kyeong Seong, Heung-Soo Kim, "A Study on the Design of Highly Parallel Multiplier using VCGM," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 6, pp. 555-561, 6. 2002.