Design of an Area-Efficient Architecture for Block-wise MAP Turbo Decoder 


Vol. 27,  No. 8, pp. 725-732, Aug.  2002


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  Abstract

Block-wise MAP (Maximum A Posteriori) decoding algorithm for turbo-codes requires less memory than Log-MAP decoding algorithm. The BER (Bit Error Rate) performance of previous block-wise MAP decoding algorithms depend on the block length and training length. To maximize hardware utilization and perform successive decoding, the block length is set to be equal to the training length in previous MAP decoding algorithms. Simulation result on the BER performance shows that the BER performance can be maintained with shorter blocks when training' length is sufficient.
This paper proposes an architecture for area efficient block-wise MAP decoder. The proposed architecture employs the decoding scheme for reducing memory by using the training length, which is N times larger than block length. To efficiently handle the proposed scheme, a pipelined architecture is proposed. Simulation results show that memory usage can be reduced by 30%~45% in the proposed architecture without degrading the BER performance.

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  Cite this article

[IEEE Style]

M. Kang, S. Kim, S. Hwang, "Design of an Area-Efficient Architecture for Block-wise MAP Turbo Decoder," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 8, pp. 725-732, 2002. DOI: .

[ACM Style]

Moon-jun Kang, Sik Kim, and Sun-young Hwang. 2002. Design of an Area-Efficient Architecture for Block-wise MAP Turbo Decoder. The Journal of Korean Institute of Communications and Information Sciences, 27, 8, (2002), 725-732. DOI: .

[KICS Style]

Moon-jun Kang, Sik Kim, Sun-young Hwang, "Design of an Area-Efficient Architecture for Block-wise MAP Turbo Decoder," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 8, pp. 725-732, 8. 2002.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880