A 8192-point pipelined FFT/IFFT processor using two-step convergent block floating-point scaling technique 


Vol. 27,  No. 10, pp. 963-972, Oct.  2002


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  Abstract

An 8192-point pipelined FFfT/IFFT processor core is designed, which can be used in multi-carrier modulation systems such as DMT-based VDSL modem and OFDM-based DVB system. In order to improve the signal-to- quantization-noise ratio (SQNR) of FFT/IFFT results, two-step convergent block floating-point (TS_CBFP) scaling is employed. Since the proposed TS_CBFP scaling does not require additional buffer memory, it reduces memory as much as about 80% when compared with conventional CBFP methods, resulting in area- and power-efficient implementation. The SQNR of about 60-dB is achieved with IO-bit input, 14-bit internal data and twiddle factors, and 16-bit output. The core synthesized using 0.25-/㎛ CMOS library has about 76,300 gates, 390K bits RAM, and twiddle factor ROM of 39K bits. Simulation results show that it can safely operate up to 50-MHz clock frequency at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every I 64-㎲. It was verified by Xilinx FPGA implementation.

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  Cite this article

[IEEE Style]

S. Lee, D. Yang, K. Shin, "A 8192-point pipelined FFT/IFFT processor using two-step convergent block floating-point scaling technique," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 10, pp. 963-972, 2002. DOI: .

[ACM Style]

Seung-Ky Lee, Dae-Sung Yang, and Kyung-Wook Shin. 2002. A 8192-point pipelined FFT/IFFT processor using two-step convergent block floating-point scaling technique. The Journal of Korean Institute of Communications and Information Sciences, 27, 10, (2002), 963-972. DOI: .

[KICS Style]

Seung-Ky Lee, Dae-Sung Yang, Kyung-Wook Shin, "A 8192-point pipelined FFT/IFFT processor using two-step convergent block floating-point scaling technique," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 10, pp. 963-972, 10. 2002.