Fast-Serial Finite Field Multiplier without increasing the number of registers 


Vol. 27,  No. 10, pp. 973-979, Oct.  2002


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  Abstract

In this paper, an efficient architecture for the finite field multiplier is proposed. This architecture is faster and smaller than any other LFSR architectures. The traditional LFSR architecture need t x m registers for achieving the t times speed. But, we desinged the multiplier using a novel fast architecture without increasing the number of registers. The proposed multiplier is verified with a VHDL description using SYNOPSYS simulator. The measured results show that the proposed multiplier is 2 times faster than the serial LFSR multiplier. The proposed multiplier is expected to become even more advantageous in the smart card cryptography processors.

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  Cite this article

[IEEE Style]

K. Lee, W. Kim, J. Chang, Y. Bae, H. Cho, "Fast-Serial Finite Field Multiplier without increasing the number of registers," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 10, pp. 973-979, 2002. DOI: .

[ACM Style]

Kwang-Youb Lee, Won-Jong Kim, June-Young Chang, Young-Hwan Bae, and Han-Jin Cho. 2002. Fast-Serial Finite Field Multiplier without increasing the number of registers. The Journal of Korean Institute of Communications and Information Sciences, 27, 10, (2002), 973-979. DOI: .

[KICS Style]

Kwang-Youb Lee, Won-Jong Kim, June-Young Chang, Young-Hwan Bae, Han-Jin Cho, "Fast-Serial Finite Field Multiplier without increasing the number of registers," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 10, pp. 973-979, 10. 2002.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880