ASIC Implementation of Synchronization Circuit with Lossless Data Compensation 


Vol. 27,  No. 10, pp. 980-986, Oct.  2002


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  Abstract

In the fast data communication system, synchronized by a clock source, the loss of data will often occur due to several reasons as a differential routing path between data and clock, a differential propagation delay of components or an unstable phase of clock and data by external noise. In this paper, we describe the ASIC implementation of the data compensation circuit which can detect the data loss from above problems and recovery to original data with stable synchronization. EspecialIy It supports a strong stability and a good BER in the communication system for fast data transfer as optic area. This circuit is implemented by Verilog HDL and available to the digital ASIC implementations related to fast data transfer.

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  Cite this article

[IEEE Style]

J. Choi, H. Kang, M. Jun, "ASIC Implementation of Synchronization Circuit with Lossless Data Compensation," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 10, pp. 980-986, 2002. DOI: .

[ACM Style]

Jin-ho Choi, Ho-Yong Kang, and Moon-Seog Jun. 2002. ASIC Implementation of Synchronization Circuit with Lossless Data Compensation. The Journal of Korean Institute of Communications and Information Sciences, 27, 10, (2002), 980-986. DOI: .

[KICS Style]

Jin-ho Choi, Ho-Yong Kang, Moon-Seog Jun, "ASIC Implementation of Synchronization Circuit with Lossless Data Compensation," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 10, pp. 980-986, 10. 2002.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880