A low-power systolic structure for MP3 IMDCT using addition and shift operation 


Vol. 29,  No. 10, pp. 1451-1459, Oct.  2004


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  Abstract

In this paper, a low-power 32-point IMDCT structure is proposed for MP3 Through re-odering of IMDCT matrices, we propose the systolic structure operating with 16, 8, 4, 2, and 1 cycle, respectively To reduce power consumption, multiplication of each sub blocksare implemented by add and shift operation With CSD(Canonic signed digit) form coefficients To reduce, furthermore, the number of adders, we utilize the common sub-expression sharing techniques With these techniques, the relative power consumption of the proposed structure is reduced by 58.4% comparison to the conventional structure using only 2's complement form coefficient. Vali야ty of the proposed structure is proved through Verilog-HDL coding.

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  Cite this article

[IEEE Style]

Y. Jang and W. Lee, "A low-power systolic structure for MP3 IMDCT using addition and shift operation," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 10, pp. 1451-1459, 2004. DOI: .

[ACM Style]

Young-Boom Jang and Won-Sang Lee. 2004. A low-power systolic structure for MP3 IMDCT using addition and shift operation. The Journal of Korean Institute of Communications and Information Sciences, 29, 10, (2004), 1451-1459. DOI: .

[KICS Style]

Young-Boom Jang and Won-Sang Lee, "A low-power systolic structure for MP3 IMDCT using addition and shift operation," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 10, pp. 1451-1459, 10. 2004.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880