Using Parallel SISO Decoders 


Vol. 30,  No. 2, pp. 25-30, Feb.  2005


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  Abstract

Turbo code is popularly used for the reliable communication in the presence of burst errors. Even if it shows good error performance near to the Shannon limits, it requires a large amount of memories and exhibits long latency. This paper proposes an architecture for the low power implementation of the Turbo decoder adopting the Max-Log-Map algorithm. In the proposed design, two SISO decoders are designed to operate in parallel, and a novel interleaver is designed to prevent the collision of memory accesses by two SISO decoders. Experimental results show that power consumption has been reduced by about 40% in the proposed decoder compared to previous Turbo decoders. The area overhead due to the additional interleaver controller is negligible.

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  Cite this article

[IEEE Style]

H. Lee and S. Hwang, "Using Parallel SISO Decoders," The Journal of Korean Institute of Communications and Information Sciences, vol. 30, no. 2, pp. 25-30, 2005. DOI: .

[ACM Style]

Hee-jin Lee and Sun-young Hwang. 2005. Using Parallel SISO Decoders. The Journal of Korean Institute of Communications and Information Sciences, 30, 2, (2005), 25-30. DOI: .

[KICS Style]

Hee-jin Lee and Sun-young Hwang, "Using Parallel SISO Decoders," The Journal of Korean Institute of Communications and Information Sciences, vol. 30, no. 2, pp. 25-30, 2. 2005.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880