A module generator for variable-precision multiplier core with error compensation for low-power DSP applications 


Vol. 30,  No. 2, pp. 129-136, Feb.  2005


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  Abstract

A multiplier generator, VPM_Gen (Variable-Precision Multiplier Generator), which generates Verilog-HDL models of multiplier cores with user-defined bit-width specification, is described. The bit-widths of operands are parameterized in the range of 8-bit~32-bit with 1-bit step, and the product from multiplier core can be truncated in the range of 8-bit~64-bit with 2-bit step, resulting that the VPM_Gen can generate 3,455 multiplier cores. In the case of truncating multiplier output, by eliminating the circuits corresponding to the truncation part, the gate counts and power dissipation can be reduced by about 40% and 30%, respectively, compared with full-precision multiplier. As a result, an area-efficient and low-power multiplier core can be obtained. To minimize truncation error, an adaptive error-compensation method considering the number of truncation bits is employed. The
multiplier cores generated by VPM_Gen have been verified using Xilinx FPGA board and logic analyzer.

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  Cite this article

[IEEE Style]

S. Hwang, J. Lee, K. Shin, "A module generator for variable-precision multiplier core with error compensation for low-power DSP applications," The Journal of Korean Institute of Communications and Information Sciences, vol. 30, no. 2, pp. 129-136, 2005. DOI: .

[ACM Style]

Seok-Ki Hwang, Jin-Woo Lee, and Kyung-Wook Shin. 2005. A module generator for variable-precision multiplier core with error compensation for low-power DSP applications. The Journal of Korean Institute of Communications and Information Sciences, 30, 2, (2005), 129-136. DOI: .

[KICS Style]

Seok-Ki Hwang, Jin-Woo Lee, Kyung-Wook Shin, "A module generator for variable-precision multiplier core with error compensation for low-power DSP applications," The Journal of Korean Institute of Communications and Information Sciences, vol. 30, no. 2, pp. 129-136, 2. 2005.