Efficient DSP Architecture for Viterbi Algorithm 


Vol. 30,  No. 3, pp. 217-225, Mar.  2005


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  Abstract

This paper presents specialized DSP instructions and their architecture for the Viterbi algorithm used in various wireless communication standards. The proposed architecture can significantly reduce the Trace Back (TB) latency. The proposed instructions perform the Add Compare Select (ACS) and TB operations in parallel and the architecture has special hardware, called the Offset Calculation Unit (OCU), which automatically calculates data addresses for the trellis butterfly computations. Logic synthesis has been performed using the Samsung SEC 0.18 ㎛ standard cell library. OCU consists of 1,460 gates and the maximum delay of OCU is about 5.75 ㎱. The BER performance of the ACS-TB parallel method increases about 0.00022dB at 6dB Eb/No compared with the typical TB method, which is negligible. When the constraint length K is 5, the proposed DSP architecture can reduce the decoding cycles about 17% compared with the Carmel DSP and about 45% compared with TMS320c55x.

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  Cite this article

[IEEE Style]

W. h. Park, M. h. Sunwoo, S. k. Oh, "Efficient DSP Architecture for Viterbi Algorithm," The Journal of Korean Institute of Communications and Information Sciences, vol. 30, no. 3, pp. 217-225, 2005. DOI: .

[ACM Style]

Weon heum Park, Myung hoon Sunwoo, and Seong keun Oh. 2005. Efficient DSP Architecture for Viterbi Algorithm. The Journal of Korean Institute of Communications and Information Sciences, 30, 3, (2005), 217-225. DOI: .

[KICS Style]

Weon heum Park, Myung hoon Sunwoo, Seong keun Oh, "Efficient DSP Architecture for Viterbi Algorithm," The Journal of Korean Institute of Communications and Information Sciences, vol. 30, no. 3, pp. 217-225, 3. 2005.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880