Design and Fabrication of 5 GHz Band MMIC Power Amplifier for Wireless LAN Applications Using Size Optimization of PHEMTs 


Vol. 31,  No. 6, pp. 634-639, Jun.  2006


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  Abstract

In this paper an MMIC 2-stage power amplifier is designed and fabricated for 5GHz wireless LAN applications using 0.5㎛ gate length PHEMT transistors. The PHEMT gate width is optimized in order to meet the linearity and efficiency of the MMIC power amplifier. The 0.5㎛ x 600㎛ PHEMT for the drive stage and 0.5㎛ x 3000㎛ PHEMT for the amplification stage are the optimized sizes to achieve more than 25㏈c of third order IMD at the power level of 3㏈ back-off from the input P1㏈ and more than 22㏈m output power under a supply voltage of 3.3V. The two-stage MMIC power amplifier is designed to be used for the both of HIPERLAN/2 and IEEE 802.11a because of its broa㏈and characteristics. The fabricated PHEMT MMIC power amplifier exhibits a 20.1㏈ linear power gain, a maximum 22㏈m output power, a 24% power added efficiency under 3.3V supply voltage. The input and output on-chip matching circuits are included on a chip of 1400x1200㎛².

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  Cite this article

[IEEE Style]

H. Park, I. Hwang, H. Yoon, "Design and Fabrication of 5 GHz Band MMIC Power Amplifier for Wireless LAN Applications Using Size Optimization of PHEMTs," The Journal of Korean Institute of Communications and Information Sciences, vol. 31, no. 6, pp. 634-639, 2006. DOI: .

[ACM Style]

Hun Park, In-Gab Hwang, and Hyung-Sik Yoon. 2006. Design and Fabrication of 5 GHz Band MMIC Power Amplifier for Wireless LAN Applications Using Size Optimization of PHEMTs. The Journal of Korean Institute of Communications and Information Sciences, 31, 6, (2006), 634-639. DOI: .

[KICS Style]

Hun Park, In-Gab Hwang, Hyung-Sik Yoon, "Design and Fabrication of 5 GHz Band MMIC Power Amplifier for Wireless LAN Applications Using Size Optimization of PHEMTs," The Journal of Korean Institute of Communications and Information Sciences, vol. 31, no. 6, pp. 634-639, 6. 2006.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880