FPGA Design of Motion JPEG2000 Encoder for Digital Cinema 


Vol. 32,  No. 3, pp. 297-305, Mar.  2007


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  Abstract

In the paper, a Motion JPEG2000 coder which has been set as the standard for image compression by the Digital Cinema Initiatives (DCI), an organization composed of major movie studios was implemented into a target FPGA. The DWT (Discrete Wavelet Transform) based on lifting and the Tier 1 of EBCOT (Embedded Block Coding with Optimized Truncation) which are major functional modules of the JPEG2000 were setup with dedicated hardware. The Tier 2 process was implemented in software. For digital cinema the tile-size was set to support 1024×1024 pixels. To ensure the real-time operations, three entropy encoders were used. When Verilog-HDL was used for hardware, resources of 32,470 LEs in Altera’s Stratix EP1S80 were used, and the hardware worked stably at the frequency of 150㎒.

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  Cite this article

[IEEE Style]

Y. Seo, H. Choi, D. Kim, "FPGA Design of Motion JPEG2000 Encoder for Digital Cinema," The Journal of Korean Institute of Communications and Information Sciences, vol. 32, no. 3, pp. 297-305, 2007. DOI: .

[ACM Style]

Young-Ho Seo, Hyun-Jun Choi, and Dong-Wook Kim. 2007. FPGA Design of Motion JPEG2000 Encoder for Digital Cinema. The Journal of Korean Institute of Communications and Information Sciences, 32, 3, (2007), 297-305. DOI: .

[KICS Style]

Young-Ho Seo, Hyun-Jun Choi, Dong-Wook Kim, "FPGA Design of Motion JPEG2000 Encoder for Digital Cinema," The Journal of Korean Institute of Communications and Information Sciences, vol. 32, no. 3, pp. 297-305, 3. 2007.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880