Design of an Automatic Generation System for Cycle-accurate Instruction-set Simulators for DSP Processors 


Vol. 32,  No. 9, pp. 931-939, Sep.  2007


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  Abstract

This paper describes the system which automatically generates instruction-set simulators cores using the SMDL. SMDL describes structure and instruction-set information of a target DSP machine. Analyzing behavioral information of each pipeline stage of all instructions on a target ASIPs, the proposed system automatically generates a cycle-accurate instruction set simulator in C++ for a target processor. The proposed system has been tested by generating instruction-set simulators for ARM9E-S, ADSP-TS20x, and TMS320C2x architectures. Experiments were performed by checking the functions of the 4x4 matrix multiplication, 16-bit IIR filter, 32-bit multiplication, and the FFT using the generated simulators. Experimental results show the functional accuracy of the generated simulators.

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  Cite this article

[IEEE Style]

S. Hong, C. Park, S. Hwang, "Design of an Automatic Generation System for Cycle-accurate Instruction-set Simulators for DSP Processors," The Journal of Korean Institute of Communications and Information Sciences, vol. 32, no. 9, pp. 931-939, 2007. DOI: .

[ACM Style]

Sung-Min Hong, Chang-Soo Park, and Sun-Young Hwang. 2007. Design of an Automatic Generation System for Cycle-accurate Instruction-set Simulators for DSP Processors. The Journal of Korean Institute of Communications and Information Sciences, 32, 9, (2007), 931-939. DOI: .

[KICS Style]

Sung-Min Hong, Chang-Soo Park, Sun-Young Hwang, "Design of an Automatic Generation System for Cycle-accurate Instruction-set Simulators for DSP Processors," The Journal of Korean Institute of Communications and Information Sciences, vol. 32, no. 9, pp. 931-939, 9. 2007.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880