A Low Complexity and A Low Latency Systolic Arrays for Multiplication in GF(2m) Using An Optimal Normal Basis of Type II 


Vol. 33,  No. 1, pp. 140-148, Jan.  2008


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  Abstract

Using the self duality of an optimal normal basis(ONB) of type II, we present a bit parallel and bit serial systolic arrays over GF(2m) which has a low hardware complexity and a low latency. We show that our multiplier has a latency m+1 and the basic cell of our circuit design needs 5 latches (flip-flops). Comparing with other arrays of the same kinds, we find that our array has significantly reduced latency and hardware complexity.

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  Cite this article

[IEEE Style]

S. Kwon, Y. K. Kwon, C. H. Kim, C. P. Hong, "A Low Complexity and A Low Latency Systolic Arrays for Multiplication in GF(2m) Using An Optimal Normal Basis of Type II," The Journal of Korean Institute of Communications and Information Sciences, vol. 33, no. 1, pp. 140-148, 2008. DOI: .

[ACM Style]

Soonhak Kwon, Yun Ki Kwon, Chang Hoon Kim, and Chun Pyo Hong. 2008. A Low Complexity and A Low Latency Systolic Arrays for Multiplication in GF(2m) Using An Optimal Normal Basis of Type II. The Journal of Korean Institute of Communications and Information Sciences, 33, 1, (2008), 140-148. DOI: .

[KICS Style]

Soonhak Kwon, Yun Ki Kwon, Chang Hoon Kim, Chun Pyo Hong, "A Low Complexity and A Low Latency Systolic Arrays for Multiplication in GF(2m) Using An Optimal Normal Basis of Type II," The Journal of Korean Institute of Communications and Information Sciences, vol. 33, no. 1, pp. 140-148, 1. 2008.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880