Design of an Efficient Coarse Frequency Estimator Using a Serial Correlator for DVB-S2 


Vol. 33,  No. 4, pp. 434-439, Apr.  2008


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  Abstract

This paper proposes an efficient coarse frequency synchronizer for digital video broadcasting - second generation (DVB-S2). The input signal requirement of acquisition range for coarse frequency estimator in the DVB-S2 is around ±1.5625Mhz, which corresponds to 6.25% of the symbol rate at 25Mbaud. At the process of analyzing the robust algorithm among data-aided approaches, we find that the Luise & Reggiannini (L&R) algorithm is the most promising one for coarse frequency estimation with respect to estimation performance and complexity. However, it requires many multipliers and adders to compute output values of correlators. We propose an efficient architecture identifying the serial correlator with the buffer and multiplexers. The proposed coarse frequency synchronizer can reduce the hardware complexity about 92% of the direct implementation. The proposed architecture has been implemented and verified on the Xilinx Virtex Ⅱ FPGA.

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  Cite this article

[IEEE Style]

H. J. Yun and M. H. Sunwoo, "Design of an Efficient Coarse Frequency Estimator Using a Serial Correlator for DVB-S2," The Journal of Korean Institute of Communications and Information Sciences, vol. 33, no. 4, pp. 434-439, 2008. DOI: .

[ACM Style]

Hyoung Jin Yun and Myung Hoon Sunwoo. 2008. Design of an Efficient Coarse Frequency Estimator Using a Serial Correlator for DVB-S2. The Journal of Korean Institute of Communications and Information Sciences, 33, 4, (2008), 434-439. DOI: .

[KICS Style]

Hyoung Jin Yun and Myung Hoon Sunwoo, "Design of an Efficient Coarse Frequency Estimator Using a Serial Correlator for DVB-S2," The Journal of Korean Institute of Communications and Information Sciences, vol. 33, no. 4, pp. 434-439, 4. 2008.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880