An Optimized Design of RS(23,17) Decoder for UWB 


Vol. 33,  No. 8, pp. 821-828, Aug.  2008


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  Abstract

In this paper, we present an optimized design of RS(23,17) decoder for UWB, which uses the pipeline structured-modified Euclidean(PS-ME) algorithm. Firstly, the modified processing element(PE) block is presented in order to get rid of degree comparison circuits, registers and MUX at the final PE stage. Also, a degree computationless decoding algorithm is proposed, so that the hardware complexity of the decoder can be reduced and high-speed decoder can be implemented. Additionally, we optimize Chien search algorithm, Forney algorithm, and FIFO size for UWB specification. Using Verilog HDL, the proposed decoder is implemented and synthesized with Samsung 65㎚ library. From synthesis results, it can operate at clock frequency of 250㎒, and gate count is 17,628.

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  Cite this article

[IEEE Style]

S. Kang and H. Kim, "An Optimized Design of RS(23,17) Decoder for UWB," The Journal of Korean Institute of Communications and Information Sciences, vol. 33, no. 8, pp. 821-828, 2008. DOI: .

[ACM Style]

Sung-jin Kang and Han-jong Kim. 2008. An Optimized Design of RS(23,17) Decoder for UWB. The Journal of Korean Institute of Communications and Information Sciences, 33, 8, (2008), 821-828. DOI: .

[KICS Style]

Sung-jin Kang and Han-jong Kim, "An Optimized Design of RS(23,17) Decoder for UWB," The Journal of Korean Institute of Communications and Information Sciences, vol. 33, no. 8, pp. 821-828, 8. 2008.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880