Implementation of High Throughput LDPC Code Decoder for DVB-S2 


Vol. 33,  No. 9, pp. 924-933, Sep.  2008


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  Abstract

This paper proposes a novel LDPC code decoder architecture to improve throughput for DVB-S2, a second generation standard of ETSI for satellite broad-band applications. The proposed architecture clusters 360 bitnodes and checknodes into groups utilizing the property of IRA-LDPC code. Functional modules which perform calculations for bitnode groups and checknode groups have local memories and store the messages from the other type of functional modules connected by edges at their local memories. The proposed architecture can avoid memory conflicts by accessing stored messages sequentially, hence, increases throughput in the proposed DVB-S2 LDPC code decoder architecture. The proposed architecture was synthesized using the TSMC 90㎚ technology. Synthesis results show that throughput of the proposed architecture is improved by 104% and 478%, respectively, when compared with those of the architectures proposed by F. Kienle and J. Dielissen.

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  Cite this article

[IEEE Style]

S. Kim, C. Park, S. Hwang, "Implementation of High Throughput LDPC Code Decoder for DVB-S2," The Journal of Korean Institute of Communications and Information Sciences, vol. 33, no. 9, pp. 924-933, 2008. DOI: .

[ACM Style]

Seong-Woon Kim, Chang-Soo Park, and Sun-Young Hwang. 2008. Implementation of High Throughput LDPC Code Decoder for DVB-S2. The Journal of Korean Institute of Communications and Information Sciences, 33, 9, (2008), 924-933. DOI: .

[KICS Style]

Seong-Woon Kim, Chang-Soo Park, Sun-Young Hwang, "Implementation of High Throughput LDPC Code Decoder for DVB-S2," The Journal of Korean Institute of Communications and Information Sciences, vol. 33, no. 9, pp. 924-933, 9. 2008.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880