Memory Access Reduction Scheme for H.264/AVC Decoder Motion Compensation 


Vol. 34,  No. 4, pp. 349-354, Apr.  2009


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  Abstract

In this paper, a new motion compensation scheme to reduce external memory access frequency which is one of the major bottlenecks for real-time decoding is proposed. Most H.264/AVC decoders store reference pictures in external memories due to the large size and reference blocks are read into the decoder core as needed during decoding. If the reference data access is done for each reference block in decoding sequence, the memory bandwidth can be unacceptable for real-time decoding. This paper presents a memory access scheme for motion compensation to read as many reference data as possible with reduced memory access frequency by analyzing reference data access pattern for each macroblock. Experimental results show that the proposed motion compensation scheme leads to approximately 30% improvement in memory bandwidth requirement.

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  Cite this article

[IEEE Style]

K. Park and Y. Hong, "Memory Access Reduction Scheme for H.264/AVC Decoder Motion Compensation," The Journal of Korean Institute of Communications and Information Sciences, vol. 34, no. 4, pp. 349-354, 2009. DOI: .

[ACM Style]

Kyoungoh Park and Youpyo Hong. 2009. Memory Access Reduction Scheme for H.264/AVC Decoder Motion Compensation. The Journal of Korean Institute of Communications and Information Sciences, 34, 4, (2009), 349-354. DOI: .

[KICS Style]

Kyoungoh Park and Youpyo Hong, "Memory Access Reduction Scheme for H.264/AVC Decoder Motion Compensation," The Journal of Korean Institute of Communications and Information Sciences, vol. 34, no. 4, pp. 349-354, 4. 2009.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880