Implementation of a High Speed GEM Frame Synchronization Circuit in the G-PON TC Sublayer Payload 


Vol. 34,  No. 5, pp. 469-479, May  2009


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  Abstract

The GEM frame is used a mean to deliver the variable length user data and consists of the header and the payload in the G-PON system. The HEC field of header protects contents of the header and is used to maintain GEM frame synchronization at the same time. When an LCDG (Loss of GEM Channel Delineation) occurs while receiving frames, the receiver have to discard corrupted frames until acquiring the synchronization again. Accordingly, high-speed synchronization method is required to minimize the frame loss. In this paper, we suggest not only a main state machine but a sub-state machine to reduce the frame loss when undetectable errors occurred in the GEM header. Also, we provide a more efficient and fast parallel structure to detect the starting point of the header. Finally, the proposed method is implemented with the FPGA and verified by the logic analyzer.

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  Cite this article

[IEEE Style]

H. Chung and Y. Kwon, "Implementation of a High Speed GEM Frame Synchronization Circuit in the G-PON TC Sublayer Payload," The Journal of Korean Institute of Communications and Information Sciences, vol. 34, no. 5, pp. 469-479, 2009. DOI: .

[ACM Style]

Hae Chung and Youngjin Kwon. 2009. Implementation of a High Speed GEM Frame Synchronization Circuit in the G-PON TC Sublayer Payload. The Journal of Korean Institute of Communications and Information Sciences, 34, 5, (2009), 469-479. DOI: .

[KICS Style]

Hae Chung and Youngjin Kwon, "Implementation of a High Speed GEM Frame Synchronization Circuit in the G-PON TC Sublayer Payload," The Journal of Korean Institute of Communications and Information Sciences, vol. 34, no. 5, pp. 469-479, 5. 2009.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880