Design of Digital Circuit on Heterogeneous Adder using Delay/Area Design Space Search 


Vol. 34,  No. 10, pp. 305-309, Oct.  2009


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  Abstract

The adder is the most frequently used arithmetic unit in the digital system. Calculation speed depends on the carrying method of the adder. Without the calculation speed satisfying the digital system designer and the adder of the circuit area, the circuit area of the adder calculation unit becomes wider and the cost will increase. In this paper we search the designer space of the adder calculation unit using the adder in the process of designing the digital system. When we search the optimal adder, we propose a designing process for the digital system.

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  Cite this article

[IEEE Style]

Y. Na, "Design of Digital Circuit on Heterogeneous Adder using Delay/Area Design Space Search," The Journal of Korean Institute of Communications and Information Sciences, vol. 34, no. 10, pp. 305-309, 2009. DOI: .

[ACM Style]

Young-nam Na. 2009. Design of Digital Circuit on Heterogeneous Adder using Delay/Area Design Space Search. The Journal of Korean Institute of Communications and Information Sciences, 34, 10, (2009), 305-309. DOI: .

[KICS Style]

Young-nam Na, "Design of Digital Circuit on Heterogeneous Adder using Delay/Area Design Space Search," The Journal of Korean Institute of Communications and Information Sciences, vol. 34, no. 10, pp. 305-309, 10. 2009.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880