LDPC Decoder Architecture for High-speed UWB System 


Vol. 35,  No. 3, pp. 287-294, Mar.  2010


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  Abstract

MB-OFDM UWB system will adopt LDPC codes to enhance the decoding performance with higher data rates. In this paper, we will consider algorithm and architecture of the LDPC codes in MB-OFDM UWB system. To suggest the hardware efficient LDPC decoder architecture, LLR(log-likelihood-ration) calculation algorithms and check node update algorithms are analyzed. And we proposed the architecture of LDPC decoder for the high throughput application of Wimedia UWB. We estimated the feasibility of the proposed architecture by implementation in a FPGA. The implementation results show our architecture attains higher throughput than other result of QC-LDPC case. Using this architecture, we can implement LDPC decoder for high throughput transmission, but it is 0.2dB inferior to the BP algorithm.

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  Cite this article

[IEEE Style]

S. Choi, W. Lee, H. Chung, "LDPC Decoder Architecture for High-speed UWB System," The Journal of Korean Institute of Communications and Information Sciences, vol. 35, no. 3, pp. 287-294, 2010. DOI: .

[ACM Style]

Sung-Woo Choi, Woo-Yong Lee, and Hyun-Kyu Chung. 2010. LDPC Decoder Architecture for High-speed UWB System. The Journal of Korean Institute of Communications and Information Sciences, 35, 3, (2010), 287-294. DOI: .

[KICS Style]

Sung-Woo Choi, Woo-Yong Lee, Hyun-Kyu Chung, "LDPC Decoder Architecture for High-speed UWB System," The Journal of Korean Institute of Communications and Information Sciences, vol. 35, no. 3, pp. 287-294, 3. 2010.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880