A Modified Sum-Product Algorithm for Error Floor Reduction in LDPC Codes 


Vol. 35,  No. 5, pp. 423-431, May  2010


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  Abstract

In this paper, a modified sum-product algorithm to correct bit errors captured within the trapping sets, which are produced in decoding of low-density parity-check (LDPC) codes, is proposed. Unlike the original sum-product algorithm, the proposed decoding method consists of two stages. Whether the main cause of decoding failure is the trapping sets or not is determined at the first stage. And the bit errors within the trapping sets are corrected at the second stage. In the modified algorithm, the set of failed check nodes and the transition patterns of hard-decision bits are exploited to search variable nodes in the trapping sets. After inverting information of the variable nodes, the sum-product algorithm is carried out to correct the bit errors. As a result of simulation, the proposed algorithm shows continuously improved error performance with increase in the signal-to-noise ratio. It is, therefore, considered that the modified sum-product algorithm significantly reduces or possibly eliminates the error floor in LDPC codes.

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  Cite this article

[IEEE Style]

S. K. Yu, S. G. Kang, E. K. Joo, "A Modified Sum-Product Algorithm for Error Floor Reduction in LDPC Codes," The Journal of Korean Institute of Communications and Information Sciences, vol. 35, no. 5, pp. 423-431, 2010. DOI: .

[ACM Style]

Seog Kun Yu, Seog Geun Kang, and Eon Kyeong Joo. 2010. A Modified Sum-Product Algorithm for Error Floor Reduction in LDPC Codes. The Journal of Korean Institute of Communications and Information Sciences, 35, 5, (2010), 423-431. DOI: .

[KICS Style]

Seog Kun Yu, Seog Geun Kang, Eon Kyeong Joo, "A Modified Sum-Product Algorithm for Error Floor Reduction in LDPC Codes," The Journal of Korean Institute of Communications and Information Sciences, vol. 35, no. 5, pp. 423-431, 5. 2010.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880