Design of a 6bit 800MS/s CMOS A/D Converter Using Synchronizable Error Correction Circuit 


Vol. 35,  No. 5, pp. 504-512, May  2010


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  Abstract

The paper proposes the 6bit 800MS/s flash A/D converter that can be applied to wireless USB chip-set. The paper simplified the error correction circuit and synchronization block as one circuit which are used respectively, and furthermore reduced the burden on the hardware. Comparing to the conventional error correction circuit, the proposed error correction circuit in this paper reduced 5 MOS transistors, the area of each error correction circuit is reduced by 9%. The A/D converter is fabricated with 0.18um CMOS 1-poly 6-metal process, and power dissipation is 182㎽ at 0.8Vpp input range and 1.8V supply voltage. The measured result shows 4.0bit of ENOB at 800MS/s conversion rate and 128.1㎒ input frequency.

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  Cite this article

[IEEE Style]

W. Kim, J. Seon, K. Yoon, "Design of a 6bit 800MS/s CMOS A/D Converter Using Synchronizable Error Correction Circuit," The Journal of Korean Institute of Communications and Information Sciences, vol. 35, no. 5, pp. 504-512, 2010. DOI: .

[ACM Style]

Won Kim, Jong-kug Seon, and Kwang-sub Yoon. 2010. Design of a 6bit 800MS/s CMOS A/D Converter Using Synchronizable Error Correction Circuit. The Journal of Korean Institute of Communications and Information Sciences, 35, 5, (2010), 504-512. DOI: .

[KICS Style]

Won Kim, Jong-kug Seon, Kwang-sub Yoon, "Design of a 6bit 800MS/s CMOS A/D Converter Using Synchronizable Error Correction Circuit," The Journal of Korean Institute of Communications and Information Sciences, vol. 35, no. 5, pp. 504-512, 5. 2010.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880