Power-Minimizing DVFS Algorithm for a Video Decoder with Buffer Constraints 


Vol. 36,  No. 9, pp. 1082-1091, Sep.  2011


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  Abstract

Power-reduction techniques based on DVFS(Dynamic Voltage and Frequency Scaling) are crucial for lengthening operating times of battery powered mobile systems. This paper proposes an optimal DVFS scheduling algorithm for decoders with memory size limitation on display buffer, which is realistic constraints not properly touched in the previous works. Furthermore, we mathematically prove that the proposed algorithm is optimal in the limited display buffer and limited clock frequency model, and also can be used for feasibility check. Simulation results show the proposed algorithm outperformed the previous heuristic algorithms by 7% in average, and the performance of all algorithms using display buffers saturates at about 10 frame size.

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  Cite this article

[IEEE Style]

S. Jeong and H. Ahn, "Power-Minimizing DVFS Algorithm for a Video Decoder with Buffer Constraints," The Journal of Korean Institute of Communications and Information Sciences, vol. 36, no. 9, pp. 1082-1091, 2011. DOI: .

[ACM Style]

Seungho Jeong and Heejune Ahn. 2011. Power-Minimizing DVFS Algorithm for a Video Decoder with Buffer Constraints. The Journal of Korean Institute of Communications and Information Sciences, 36, 9, (2011), 1082-1091. DOI: .

[KICS Style]

Seungho Jeong and Heejune Ahn, "Power-Minimizing DVFS Algorithm for a Video Decoder with Buffer Constraints," The Journal of Korean Institute of Communications and Information Sciences, vol. 36, no. 9, pp. 1082-1091, 9. 2011.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880