Efficient VLSI Architecture for Lifting-Based 2D Discrete Wavelet Transform Filter 


Vol. 37,  No. 11, pp. 993-1000, Nov.  2012


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  Abstract

In this research, we proposed an efficient VLSI architecture of the lifting-based 2D DWT (Discrete Wavelet Transform) filter with 100% hardware utilization. The (9,7) filter structure has been applied and extendable to the filter length. We proposed a new block-based scheduling that computes the DWT for the lower levels on an “as-early-as-possible” basis, which means that the calculation for the lower level will start as soon as the data is ready. Since the proposed 2D DWT computes the outputs of all levels by one row-based scan, the intermediate results for other resolution levels should be kept in storage such as the Data Format Converter (DFC) and the Delay Control Unit (DCU) until they are used. When the size of input image is N×Nand m is the filter length, the required storage for the proposed architecture is about 2mN. Since the proposed architecture processes the 2D DWT in horizontal and vertical directions at the same time with 4 input data, the total period for 2D DWT is N²(1-2<SUP>-2J</SUP>)/3.

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  Cite this article

[IEEE Style]

T. Park and T. Park, "Efficient VLSI Architecture for Lifting-Based 2D Discrete Wavelet Transform Filter," The Journal of Korean Institute of Communications and Information Sciences, vol. 37, no. 11, pp. 993-1000, 2012. DOI: .

[ACM Style]

Taegu Park and Taegeun Park. 2012. Efficient VLSI Architecture for Lifting-Based 2D Discrete Wavelet Transform Filter. The Journal of Korean Institute of Communications and Information Sciences, 37, 11, (2012), 993-1000. DOI: .

[KICS Style]

Taegu Park and Taegeun Park, "Efficient VLSI Architecture for Lifting-Based 2D Discrete Wavelet Transform Filter," The Journal of Korean Institute of Communications and Information Sciences, vol. 37, no. 11, pp. 993-1000, 11. 2012.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880