Design of a 6-bit 500MS/s CMOS A/D Converter with Comparator-Based Input Voltage Range Detection Circuit 


Vol. 38,  No. 4, pp. 303-309, Apr.  2013


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  Abstract

A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82mW with a single power supply of 1.2V and achieves 4.9 effective number of bits for input frequency up to 1MHz at 500 MS/s. Therefore it results in 4.75pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.

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  Cite this article

[IEEE Style]

S. Dai, S. M. Lee, K. S. Yoon, "Design of a 6-bit 500MS/s CMOS A/D Converter with Comparator-Based Input Voltage Range Detection Circuit," The Journal of Korean Institute of Communications and Information Sciences, vol. 38, no. 4, pp. 303-309, 2013. DOI: .

[ACM Style]

Shi Dai, Sang Min Lee, and Kwang Sub Yoon. 2013. Design of a 6-bit 500MS/s CMOS A/D Converter with Comparator-Based Input Voltage Range Detection Circuit. The Journal of Korean Institute of Communications and Information Sciences, 38, 4, (2013), 303-309. DOI: .

[KICS Style]

Shi Dai, Sang Min Lee, Kwang Sub Yoon, "Design of a 6-bit 500MS/s CMOS A/D Converter with Comparator-Based Input Voltage Range Detection Circuit," The Journal of Korean Institute of Communications and Information Sciences, vol. 38, no. 4, pp. 303-309, 4. 2013.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880